1. Field of the Invention
The present invention relates to a delay lock loop circuit and method, and more particularly, to a delay lock loop circuit and method which feed back an inversion signal.
2. Description of the Prior Art
In the prior art, the delay lock loop (DLL) circuit utilizes N delay units to perform N stages of timing delay of an input clock source, so as to feed back a non-inversion clock source and to lock the input clock source with specific phases. Please refer to FIG. 1, which illustrates a conventional schematic diagram of a DLL circuit 10. As shown in FIG. 1, the DLL circuit 10 includes a voltage-controlled delay line (VCDL) 100, a phase/frequency detector 102, a charge pump 104 and a loop filter 106. After the VCDL 100 receives an input clock source CLK_IN, N delay units DC_1-DC_N generate the N stages of timing delay of the input clock source CLK_IN, so as to generate a feedback signal CLK_FB to the phase/frequency detector 102. The phase/frequency detector 102 simultaneously compares phase differences between the input clock source CLK_IN and the feedback signal CLK_FB, so as to output a first detection signal UP and a second detection signal DN to the charge pump 104. The charge pump 104 further generates a control voltage VC to the loop filter 106 according to the first detection signal UP and the second detection signal DN. Lastly, the loop filter 106 outputs the stabilized control voltage VC to the delay units DC_1-DC_N of the VCDL 100 as a reference, so as to output an output clock source CLK_OUT.
Therefore, in the prior art, a circuit designer has to utilize the delay units DC_1-DC_N and the feedback signal CLK_FB to realize the specific phase clock sources, which leads to a less flexible circuit design. Additionally, utilizing the delay units DC_1-DC_N results in a resolution of the specific phase clock source being 360/N, which provides less contribution to requirements of low production cost, low power consumption and high operational efficiency.